1. Field of the Invention
The present invention generally relates to integrated circuits, and more particularly to providing latchup and noise suppression in such integrated circuits.
2. Description of the Related Art
As electronic components are getting smaller and smaller along with the internal structures in integrated circuits, it is getting easier to either completely destroy or otherwise impair electronic components from latchup. Latchup is when a pnpn structure transitions from a low current high voltage state to a high current low voltage state through a negative resistance region (i.e. forming an S-Type I-V (current/voltage) characteristic).
Latchup is typically understood as occurring within a pnpn structure, or silicon controlled rectifier (SCR) structure. Interestingly enough, these pnpn structures can be intentionally designed, or even unintentionally formed between structures. Hence, latchup conditions can occur within peripheral circuits or internal circuits, within one circuit (intra-circuit) or between multiple circuits (inter-circuit).
Latchup is typically initiated by an equivalent circuit of a cross-coupled pnp and npn transistor. With the base and collector regions being cross-coupled, current flows from one device leading to the initiation of the second (“regenerative feedback”). These pnp and npn elements can be any diffusions or implanted regions of other circuit elements (e.g. P-channel MOSFETs, N-Channel MOSFETs, resistors, etc) or actual pnp and npn bipolar transistors. In CMOS, the pnpn structure can be formed with a p-diffusion in a n-well, and a n-diffusion in a p-substrate (“parasitic pnpn”). In this case, the well and substrate regions are inherently involved in the latchup current exchange between regions.
The condition for triggering a latchup is a function of the current gain of the pnp and npn transistors, and the resistance between the emitter and the base regions. This inherently involves the well and substrate regions. The likelihood or sensitivity of a particular pnpn structure to latchup is a function of spacings (e.g. Base width of the npn and base width of the pnp), current gain of the transistors, substrate resistance and spacings, the well resistance and spacings, and isolation regions.
System-on-a-chip (SOC) solutions have been used for solving the mixed signal (voltage) and radio frequency (RF) requirements of high-speed data rate transmission, optical interconnect, wireless and wired marketplaces. Each of the noted applications has a wide range of power supply conditions, number of independent power domains, and circuit performance objectives. Different power domains are established between digital, analog and radio frequency (RF) functional blocks on an integrated chip. Part of the SOC solution has resulted in different circuit and system functions being integrated into a common chip substrate. The integration of different circuits and system functions into a common chip has also resulted in solutions for ensuring that noise from one portion or circuit of the chip does not affect a different circuit within the chip.
In internal circuits and peripheral circuitry, latchup and noise are both a concern. Latchup and noise are initiated in the substrate from overshoot and undershoot phenomenon. These can be generated by CMOS off-chip driver circuitry, receiver networks, and ESD devices. In CMOS I/O circuitry, undershoot and overshoot can lead to injection in the substrate. Hence, both a p-channel MOSFET and n-channel MOSFET can lead to substrate injection. Simultaneous switching of circuitry where overshoot or undershoot injection occurs, leads to injection into the substrate which leads to both noise injection and latchup conditions. Supporting elements in these circuits, such as pass transistors, resistor elements, test functions, over voltage dielectric limiting circuitry, bleed resistors, keeper networks and other elements can be present leading to injection into the substrate. ESD elements connected to the input pad can also lead to noise injection and latchup. ESD elements that can lead to noise injection, and latchup include MOSFETs, pnpn SCR ESD structures, p+/n-well diodes, n-well-to-substrate diodes, n+ diffusion diodes, and other ESD circuits. ESD circuits can contribute to noise injection into the substrate and latchup.
Unfortunately, the designers of the circuits often fail to anticipate or recognize the appearance of parasitic pnpn structures. Even when the circuit designer does recognize or anticipate parasitic pnpn structures, the solutions for reducing the latchup tolerance often result in unnecessarily increasing the introduction of noise into the power rails.
It would, therefore, be a distinct advantage to have a method and apparatus that improved both noise suppression and latchup tolerance in an integrated circuit. It would be further advantages if the method and apparatus would be integrated into a software tool such that the tool searched for these parastic pnpn structures and automatically inserted a solution for reducing latchup and noise suppression. The present invention provides such a method and apparatus.